Are MSR registers transparently supported in the guest ?
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Are MSR registers transparently supported in the guest ?
Don't know if this should go into another forum:
is reading from/writing to the MSR registers transparently supported in the guest OS ? In particular I am thinking about the machine check related MSRs but I'd be interested to know in general. For the machine check related MSR I had the impression that they always read as zero.
Of course I am only talking about those MSRs that are actually implemented in the host CPU.
is reading from/writing to the MSR registers transparently supported in the guest OS ? In particular I am thinking about the machine check related MSRs but I'd be interested to know in general. For the machine check related MSR I had the impression that they always read as zero.
Of course I am only talking about those MSRs that are actually implemented in the host CPU.
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Re: Are MSR registers transparently supported in the guest ?
The host CPU is the only piece of host hardware that the guest OS sees and uses - in other words the CPU is not emulated. Whether these MSU registers can be written & read I don't know, but it would take only time for someone who does know to do a test to find out.
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Re: Are MSR registers transparently supported in the guest ?
Sometimes the CPU is "emulated"/"translated"/"simulated". I deliberately put these terms in quotes because I don't know what the appropriate terminology is. Sometimes because of a workaround, sometimes because they have to work with the least common denominator (even if it's missing the latest and greatest feature), sometimes because the guest OS requires it (think OSX that I know, at least).
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Re: Are MSR registers transparently supported in the guest ?
What does "transparently" mean in this context?
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Re: Are MSR registers transparently supported in the guest ?
With "transparently" I meant that either RDMSR and WRMSR executed in the guest are executed directly on the CPU or that RDMSR and WRMSR executed in the guest are emulated in a way that they behave similarly or identical to executing them directly on the CPU.
I was talking about these MSRs (the "least common denominator" for Intel and AMD CPUs I think):
179h - IA32_MCG_CAP
17Ah - IA32_MCG_STATUS
17Bh - IA32_MCG_CTL (optional, indicated by IA32_MCG_CAP)
400h+(n*4) - IA32_MCn_CTL
401h+(n*4) - IA32_MCn_STATUS
402h+(n*4) - IA32_MCn_ADDR
additionally:
1Bh - IA32_APIC_BASE
I have implemented a machine exception handler for the guest OS and just wanted to make sure it does not lead to odd effects when the exception handler is installed in a virtual machine (in case someone has it installed in the guest OS). When I check the feature flags I get reported back that MCE and MCA bits are set but when I go ahead and read IA32_MCG_CAP I just get an "all zeros" returned, meaning no error banks and also no global IA32_MCG_CTL register.
(Additionally, I need IA32_APIC_BASE to find the APIC address in order to program the APIC to send an IPI to all CPU cores for machine check MSR set up and reprogramming CR4 which works ok.)
The return from reading IA32_MCG_CAP does not seem to make much sense which is why I thought that not all MSRs are supported or such.
If that matters: in order to do limited testing on the machine check exception handler I just executed "int 18" SW interrupt from Ring 0.
I don't know if that has a bearing on the problem.
I was talking about these MSRs (the "least common denominator" for Intel and AMD CPUs I think):
179h - IA32_MCG_CAP
17Ah - IA32_MCG_STATUS
17Bh - IA32_MCG_CTL (optional, indicated by IA32_MCG_CAP)
400h+(n*4) - IA32_MCn_CTL
401h+(n*4) - IA32_MCn_STATUS
402h+(n*4) - IA32_MCn_ADDR
additionally:
1Bh - IA32_APIC_BASE
I have implemented a machine exception handler for the guest OS and just wanted to make sure it does not lead to odd effects when the exception handler is installed in a virtual machine (in case someone has it installed in the guest OS). When I check the feature flags I get reported back that MCE and MCA bits are set but when I go ahead and read IA32_MCG_CAP I just get an "all zeros" returned, meaning no error banks and also no global IA32_MCG_CTL register.
(Additionally, I need IA32_APIC_BASE to find the APIC address in order to program the APIC to send an IPI to all CPU cores for machine check MSR set up and reprogramming CR4 which works ok.)
The return from reading IA32_MCG_CAP does not seem to make much sense which is why I thought that not all MSRs are supported or such.
If that matters: in order to do limited testing on the machine check exception handler I just executed "int 18" SW interrupt from Ring 0.
I don't know if that has a bearing on the problem.
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Re: Are MSR registers transparently supported in the guest ?
No, never.erdmann wrote:With "transparently" I meant that either RDMSR and WRMSR executed in the guest are executed directly on the CPU
Some. The machine check MSRs are not among those. A VM will never get machine checks, faulty hardware is something for the host OS to handle.or that RDMSR and WRMSR executed in the guest are emulated in a way that they behave similarly or identical to executing them directly on the CPU.
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Re: Are MSR registers transparently supported in the guest ?
Ok, that explains what I am seeing. You control MSR access via MSR bitmap, correct ? Am I assuming correctly that you return with eax=0 and edx=0 for every RDMSR that is blocked by the MSR bitmap ?
Yes, machine checks should be handled by the host.
Yes, machine checks should be handled by the host.
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Re: Are MSR registers transparently supported in the guest ?
I don't know if this will help, but seing that you're digging in much further than the average user, the Virtualbox source code is available here: https://www.virtualbox.org/wiki/Downloads
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Re: Are MSR registers transparently supported in the guest ?
Not quite, but for some MSRs that's the case. Others are completely emulated, like APIC MSRs. That is, they are blocked by the MSR bitmap and cause VM exits, but their behavior is emulated.erdmann wrote:Am I assuming correctly that you return with eax=0 and edx=0 for every RDMSR that is blocked by the MSR bitmap ?
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Re: Are MSR registers transparently supported in the guest ?
That's interesting.
Do you emulate IA32_APIC_BASE so that you can limit/remap the APIC physical address to 32-bits in case you want to run a 32-bit guest OS (like OS/2 that is limited to 32-bit physical addresses in all its public programming interfaces) under a 64-bit host OS (which might map the APIC above 4 GB physical address boundary) ?
Do you emulate IA32_APIC_BASE so that you can limit/remap the APIC physical address to 32-bits in case you want to run a 32-bit guest OS (like OS/2 that is limited to 32-bit physical addresses in all its public programming interfaces) under a 64-bit host OS (which might map the APIC above 4 GB physical address boundary) ?
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Re: Are MSR registers transparently supported in the guest ?
Actually no OS we know of remaps the APIC. Most SMP OSes are old enough to support the Pentium/Pentium MMX, which could not relocate the local APIC at all.