Re: Windows 8?
Posted: 21. Sep 2012, 06:41
The VM definition is attached as an XML file to make it readable.
Code: Select all
AMD Athlon(tm) 64 X2 Dual Core Processor 6000+
AMD64 Family 15 Model 107 Stepping 2, AuthenticAMD
Host VM
HTT * - Hyperthreading enabled
HYPERVISOR - - Hypervisor is present
VMX - - Supports Intel hardware-assisted virtualization
SVM * - Supports AMD hardware-assisted virtualization
EM64T * * Supports 64-bit mode
SMX - - Supports Intel trusted execution
SKINIT - - Supports AMD SKINIT
EIST - - Supports Enhanced Intel Speedstep
NX * * Supports no-execute page protection
PAGE1GB - - Supports 1 GB large pages
PAE * * Supports > 32-bit physical addresses
PAT * * Supports Page Attribute Table
PSE * * Supports 4 MB pages
PSE36 * * Supports > 32-bit address 4 MB pages
PGE * * Supports global bit in page tables
SS - - Supports bus snooping for cache operations
VME * * Supports Virtual-8086 mode
FPU * * Implements i387 floating point instructions
MMX * * Supports MMX instruction set
MMXEXT * - Implements AMD MMX extensions
3DNOW * * Supports 3DNow! instructions
3DNOWEXT * * Supports 3DNow! extension instructions
SSE * * Supports Streaming SIMD Extensions
SSE2 * * Supports Streaming SIMD Extensions 2
SSE3 * * Supports Streaming SIMD Extensions 3
SSSE3 - - Supports Supplemental SIMD Extensions 3
SSE4.1 - - Supports Streaming SIMD Extensions 4.1
SSE4.2 - - Supports Streaming SIMD Extensions 4.2
AES - - Supports AES extensions
AVX - - Supports AVX intruction extensions
FMA - - Supports FMA extensions using YMM state
MSR * * Implements RDMSR/WRMSR instructions
MTTR * * Supports Memory Type Range Registers
XSAVE - - Supports XSAVE/XRSTOR instructions
OSXSAVE - - Supports XSETBV/XGETBV instructions
CMOV * * Supports CMOVcc instruction
CLFSH * * Supports CLFLUSH instruction
CX8 * * Supports compare and exchange 8-byte instructions
CX16 * - Supprots CMPXCHG16B instruction
DCA - - Supports prefetch from memory-mapped device
F16C - - Supports half-precision instruction
FXSR * * Supports FXSAVE/FXSTOR instructions
FFXSR * * Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - - Supports MONITOR and MWAIT instructions
MOVBE - - Supports MOVBE instruction
PCLULDQ - - Supports PCLMULDQ instruction
POPCNT - - Supports POPCNT instruction
SEP * * Supports fast system call instructions
DE * * Supports I/O breakpoints including CR4.DE
DTES64 - - Can write history of 64-bit branch addresses
DS - - Implements memory-resident debug buffer
DS-CPL - - Supports Debug Store feature with CPL
PCID - - Supports PCIDs and settable CR4.PCIDE
PDCM - - Supports Performance Capabilities MSR
RDTSCP * * Supports RDTSCP instruction
TSC * * Supports RDTSC instruction
TSC-DEADLINE - - Local APIC supports one-shot deadline timer
TSC-INVARIANT * * TSC runs at constant rate
xTPR - - Supports disabling task priority messages
ACPI - - Implements MSR for power management
TM - - Implements thermal monitor circuitry
TM2 - - Implements Thermal Monitor 2 control
APIC * * Implements software-accessible local APIC
x2APIC - - Supports x2APIC
CNXT-ID - - L1 data cache mode adaptive or BIOS
MCE * * Supports Machine Check, INT18 and CR4.MCE
MCA * * Implements Machine Check Architecture
PBE - - Supports use of FERR#/PBE# pin
PSN - - Implements 96-bit processor serial number
Host VM
Logical to Physical Processor Map: Logical to Physical Processor Map:
*- Physical Processor 0 * Physical Processor 0
-* Physical Processor 1
Logical Processor to Socket Map:
Logical Processor to Socket Map: * Socket 0
** Socket 0
Logical Processor to NUMA Node Map:
Logical Processor to NUMA Node Map: * NUMA Node 0
** NUMA Node 0
Logical Processor to Cache Map:
Logical Processor to Cache Map: * Data Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
*- Data Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64 * Instruction Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
*- Instruction Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64 * Unified Cache 0, Level 2, 512 KB, Assoc 16, LineSize 64
*- Unified Cache 0, Level 2, 512 KB, Assoc 16, LineSize 64
-* Data Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64 Logical Processor to Group Map:
-* Instruction Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64 * Group 0
-* Unified Cache 1, Level 2, 512 KB, Assoc 16, LineSize 64
Logical Processor to Group Map:
** Group 0
Now I've found the solution of my problem that BIOS didn't have NX bit setting.tpskinner wrote:From recent posts it appears that it is clear that VB does not detect that NX is enabled on a CPU where it is. Let me stress what I have said and what the other recent poster has said, "Windows 8 boots on the native hardware." That clearly means that NX is enabled on the host machines BIOS. There is no option to turn it off on my BIOS either and I am no newbie either.
Hopefully the VB developers will take note that this issue is not specific to only one CPU as I am using a different CPU from the previous poster.
Tom
From Wikipedia: "Windows 8 is slated for general availability on October 26, 2012." Unless my watch is very far off, that's almost a month from now.saberman wrote:Windows 8 has been released.
How much is Windows 8 support in VirtualBox worth to you? Is it safe to assume that it's $0?When will VirtualBox support Windows 8?